1. Field of the Invention
The invention relates to an integrated electrostatic discharge (ESD) protection circuit, and more particularly to a low voltage trigger circuit utilizing parasitic devices for protecting from ESD.
2. Description of the Related Art
The protection of integrated circuits from electrostatic discharge (ESD) is a subject which has received a lot of attention from circuit designers because of the serious damage that ESD can wreak as device dimensions are reduced. Workers in the field and inventors have proposed many solutions, many trying to solve the problem of protecting sub-micron devices while still allowing them to function unencumbered and without undue, or zero, increase of silicon real estate. The scaling down of CMOS technology into the deep submicron area of 0.25 micron and below has greatly degraded the robustness of the CMOS integrated circuits (IC).
A conventional ESD design typically consists of a two stage network, the first network comprising diodes, n- or p-channel transistors (NMOS or PMOS), and the second network comprising silicon controlled rectifiers (SCRs). The first stage should have the characteristics of fast transit time (turn on) and low trigger voltage. Because SCRs have a slower turn on and require a relatively high trigger voltage, the first stage is needed in order to provide a successful ESD protection. Thus, the performance of the first stage becomes important. Fast transit and low trigger voltage are the key criterion.
Typical circuits of the related art are shown in FIGS. 1 and 2 and will be discussed next. Turning now to FIG. 1, we show an input pad 1 connected via resistors R1 and R2 to internal circuit 2. A p-channel transistor 11 is connected between voltage supply 18 (V.sub.dd) and the junction of resistors R1 and R2. A second p-channel transistor 12 is connected between voltage supply 18 and Point X, the input to internal circuit 2. The gates of both transistors 11 and 12 are tied to voltage supply 18. An n-channel transistor 13 is connected between the junction of resistors R1/R2 and voltage supply 19, V.sub.SS, typically ground. A second n-channel transistor is connected between Point X and voltage supply 19. The gates of n-channel transistors 13 and 14 are also tied to voltage supply 19. Transistors 11 to 14 function as diodes since their gates are tied to their source. Two SCRs 15 and 16 are connected between V.sub.dd and V.sub.ss, their junctions tied to Point X.
The circuit between input pad 1 and internal circuit 2 protects internal circuit 2 from ESD pulses in the following way,
If there is a positive signal at input pad 1, which is about 0.6 Volt higher than V.sub.dd, then transistors 11 and 12 turn on, and current will be discharged through them to V.sub.dd. If there is a negative signal at input pad 1, which is about 0.6 Volt lower than ground, then transistors 13 and 14 turn on, and current will be discharged through them to ground. The current through R2 will raise or lower the potential at Point X which will trigger either SCR network 15 or 16 to further discharge the current and, therefore, protect the internal circuit 2.
Turning now to FIG. 2, we show an input pad 1 connected via resistor R1 and R2 to internal circuit 2. A diode string 21 of two diodes is connected between voltage supply 18 (V.sub.dd) and the junction of resistors R1 and R2. A second diode string 22 is connected between voltage supply 18 and Point X, the input to internal circuit 2. The cathodes of diode strings 21 and 22 are connected to voltage supply 18, and the anodes are connected to either end of resistor R2. Similarly, a third diode string 23 is connected between the junction of resistors R1/R2 and voltage supply 19 (V.sub.ss), typically ground, and a fourth diode string 24 is connected between Point X and voltage supply 19. The cathodes of diode strings 23 and 24 are connected to either end of resistor R2, and the anodes are to tied to voltage supply 19. Two SCRs 15 and 16 are connected between V.sub.dd and V.sub.ss, their junctions tied to Point X.
The circuit between input pad 1 and internal circuit 2 protects internal circuit 2 from positive ESD pulses at input pad 1 in a similar way as described for FIG. 1. If there is a positive signal at input pad 1, which is about 1.2 Volt (two diode drops) higher than V.sub.dd, then diode strings 21 and 22 become forward biased, and current will be discharged through them to V.sub.dd. A negative signal at input pad 1 about 1.2 Volt lower than ground turns on diode strings 23 and 24 and current will be discharge through them to ground. The response of Point X and SCRs 15 and 16 is identical to the description for FIG. 1.
The disadvantages of the circuits of FIGS. 1 and 2 are that the discharge capabilities of transistors 11 to 14 and diodes 21 to 24 are limited. In order to increase the current capabilities these components would have to be made larger, which also increases their parasitic capacitances and consequently slows down their response.
U.S. Patents which relate to the subject of ESD protection for integrated circuits are:
U.S. Pat. No. 5,917,336 (Smith et al.) teaches an electrostatic discharge (ESD) circuit that provides robust protection to an input/output driver circuit. The discharge path is provided by a bipolar transistor. A combination of an n-type MOSFET, a string of diodes, and a biasing circuit trigger the bipolar device. The trigger point of the MOSFET is programmable by varying the number of individual diodes in the string of diodes. The relatively high transconductance of the n-type MOSFET allows the use of a smaller ESD circuit for a given degree of protection. PA0 U.S. Pat. No. 5,530,612 (Maloney) describes a bias network in ESD protection device. The bias network is used to augment the diode string to distribute small but significant forward current to the diodes. Also employed is the use of cantilever diodes, which provide PNP Darlington gain block for ESD protection. Also described is a termination that supplies final base current to the gain block for a limited amount of time, so that ESD charge can be shunted harmlessly through the PNP chain, but assures that the structure draws no current from a stable power supply long term. PA0 U.S. Pat. No. 5,631,793 (Ker et al.) illustrates a capacitor-couple electrostatic discharge (ESD) protection circuit for protecting an internal circuit and/or an output buffer of an IC from being damaged by an ESD current. The capacitor-couple ESD protection circuit includes an ESD bypass device for bypassing the ESD current, a capacitor-couple circuit for coupling a portion of voltage to the ESD bypass device, and a potential leveling device for keeping an ESD voltage transmitted for the internal circuit at a low potential level.
It should be noted that none of the above-cited examples of the related art combine a) the low trigger voltage and fast transit characteristics of a first stage network utilizing Zener diodes and MOS transistors with b) the discharge capabilities of parasitic bipolar transistors (SCRs) of the second network and c) the low device count. The preferred embodiment of the present invention described subsequently provides all of these important features.